The JePPIX Pilot Line scales from a handful of laboratory proof-of-concept chips to many dedicated wafers of production-ready circuits. This process is quality-gated using a checklist, with managed design cycles. The outcome is a qualified design that can be reliably produced at an agreed price, delivery schedule and performance.
Dedicated wafers are used in combination with generic manufacturing processes and calibrated test and design tools. The manufacturing-grade process design kit is extracted from the generic process flow. It is used at the design stage. Following a Design Rule Check using the PDK, the design is made compliant with the foundry
process flow. Production tolerances are visible upfront for critical-to-quality parameters. The JePPIX Pilot Line can be understood as a structured program with three stage gates for optimization, validation and verification of the new circuit design.
The entry point for the JePPIX Pilot Line is an initial circuit designed for the new product. This may be a one-off experiment using MPW services, and therefore nothing is known about the reproducibility of the design.
In this optimization phase, a prototype design is identified which is tolerant to manufacture. The product requirements are clearly elaborated. The critical-to-quality parameters are identified and a range of design variations are analysed to understand the sensitivities of the design to the manufacturing process. The number of design cycles will depend on circuit complexity. The outcome is a design with quantified tolerance to manufacturing variations. TRL5 is achieved by a design of experiments (DOE) in order to find the optimized design. This can
possibly be run on different wafers using foundry process variations. Preliminary reliability tests are performed. The goal is to find the sweet spot in the DOE domain. The final maskset is a deliverable of this phase. Samples can be used at customer labs for initial integration and feasibility study.
The manufacturable design is now identified and frozen. The wafer layout is adjusted accordingly and testing methods are scaled up to better analyse functional yield. The selected design is studied for manufacturability and is shown to consistently meet the pre-agreed known-good-die requirements for the product. Functional testing shows that the end product requirements can now be met. To achieve TRL6, more wafers are run to acquire statistics. Test should be fully defined at this phase. It is the
last phase at which the customer cannot make commercial use of the PICs. The list of parameters targets and limits should be finalized at this phase. Reliability tests should all be covered at this phase, in addition to lifetime experiments. Samples can be used at customer labs for integration and feasibility study. They can also be delivered to end user for integration at system level and initial validations.
The design is now produced in pilot production quantities. This will involve multiple wafer starts to provide the statistics needed for defining manufacturing guarantees and commercial terms. Reproducible manufacturing is now demonstrated for the matured design. The development phase is completed and the foundry is able to define and agree terms for future production. This is TRL7. All delivered devices have to meet all key performance indicators. The device must match customer end-product requirements. A complete reliability report is created. The final FMEA is delivered. At the end of this phase, the process flow is frozen and the POR (Process of Record) is agreed with the customer.