A perspective on the scaling of Photonic Integrated Circuits with indium phosphide technology

In order to make Photonic Integrated Circuits (PICs) scalable and enhance their functionality, they should contain a rich mix of passive and active components. Passive components – such as filters, modulators, and antennas – are used to direct or change the properties of light. Active components, on the other hand, have the ability to sense or produce light. Examples are lasers, amplifiers, and photodetectors. While the number of components on a single photonic chip is approaching one million, most of these components are passive rather than active. Yi Wang is a Postdoctoral Researcher in the Photonic Integration research group at Eindhoven University of Technology. In the April issue of APL Photonics, he offers a perspective on the challenge this presents for the functional scaling of PICs with miniaturized active and passive components.

Scaling bottleneck

Yi explains that “the scaling bottleneck is there because the active components don’t scale at the same pace as the passive ones”. The consequence is that although photonic chips are scaling in terms of the sheer component count, their functionality is not. For applications such as LiDAR (Light Detection and Ranging), optical switches, and optical computing to be successful, PICs need either high optical power or low optical loss. Such can be realized with on-chip light generation and amplification; a functionality that can only be obtained if the integration of active components catches up with that of passives.

Graph of the total component count on PICs from 1980 onwards


In his PhD research, Yi explored various ways to enhance the performance and efficiency of active components on indium phosphide (InP) photonic chips, as reported in an article published on the TU/e website. Contrary to silicon (Si) and silicon nitride (SiN), InP has the ability to produce light, thus allowing for the fabrication of active components. “InP is a promising material when it comes to integrating active and passive components on the same chip,” Yi says. “We want and need to use InP to offer a potential solution to the scaling of PICs, regardless of the substrate material.”

IMOS technology

At the same time, the use of InP presents a challenge. Components made of this material are relatively big, which makes it hard to keep up with the ‘Moore’s Law in photonics’. Yi explains: “Similar to microelectronics, to scale up the circuit, the component sizes must be scaled down.” To tackle this challenge, Yi and his colleagues use a technology called IMOS: InP Membrane on Silicon. The critical aspect of this platform is that instead of in a bulk substrate, the components are realized in a membrane thinner than one micrometer, thereby allowing drastic miniaturization.

Yi Wang in the TU/e NanoLab


In addition to component miniaturization, membrane-based platforms such as IMOS offer powerful scaling perspectives through the elimination of unused chip areas. This means optimizing the ‘floorplan’ of a PIC: the way the components are connected and how much space these connections take without interference between components. “Ideally, you want a chip full of functional components with little to no wasted space,” Yi says. “By using advanced epitaxy techniques available with the InP technology, we can reduce the space needed for active and passive interconnections.”

If you are interested in Yi’s full perspective on how IMOS and other membrane-based platforms offer a route towards the sustained scaling of PICs, check out his article in APL Photonics: Scaling Photonic Integrated Circuits with InP technology: a perspective. You can also read his PhD thesis: InP membrane photonics for large-scale integration.

Click here if you would like to know more about IMOS and/or would like to participate in an IMOS MPW run.