Technobis PIC testing service is offered based on the prerequisite that chip design is in accordance with the generic test package design rules ASPIC General Design Rules (For Standard G5) which can be downloaded from JePPIX website or Technobis website.
In the standard offer, the following items are included, with the corresponding boundary conditions:
1) Visual inspection to identify optical I/O damage, waveguide interruptions, metallization not appropriate for wirebonding
Boundaries: Not applicable
Required input from customer: Not applicable.
2) IV curve (both forward- and reverse- biased) of max. 5 building blocks (e.g. SOA etc)
a) Forward: Max +1A or +2V (the one that is reached first)
b) Reversed biased: standard is min -3V (can go lower to -10V on request)
Inputs from customers:
c) Specifications of the desired limits on forward and reverse biases current and voltage
3) Probing one optical I/O with single fiber (SM/PM) in one of the following two ways:
a) Biasing max.5 building blocks (e.g. SOA/phase shifter/etc) to record the output spectrum
i) Biasing the same as 2a and 2b
ii) Setpoint temperature of 25°C (±10°C on request)
Inputs from the customers:
i) Choose one fixed current/voltage setpoint for all the probed building blocks
ii) Alignment of slow axis (to TE or TM of chip)
iii) Setpoint temperature during test
Other than Generic Test Package, Technobis offers dedicated package design which is more suitable for volume packaging. A highly automatic packaging line has been established to handle mid-to-high- volume.
ADDITIONAL PRODUCT SPECIFICATIONS
You can find the offers of packaging from Technobis and information of their packaging templates here: