Design Flow

Process Design Kits

Process design kits (PDKs) are defined for each foundry. These are connected to commercial software packages to enable designers to create sophisticated photonic integrated circuits in a coherent design flow. The design kit includes

  • Design rules and mask layer information
  • Library of validated and parameterized components (for circuit design) 
  • Simulation models and measurements data (passive and active building blocks BBs) 
  • Die and package templates

1. Circuit function and platform selection

Designers start from a functional requirement, and then identify the Building Blocks which are needed to enable and evaluate this function in one chip. The most appropriate platform can usually be identified by inspecting the building block performance published here. Further information may also be available from the JePPIX coordinator.

 

2. Circuit design

Designers can develop their own understanding of the design possibilities and create their own chip layouts. JePPIX partners provide regular training sessions for MPW customers, both for specific CAD tools, and also as coherent JePPIX training events. Training events are organized throughout the year in three formats

  • JePPIX flagship two-week PIC designer training event in Eindhoven, NL each fall
  • One week PIC designer training events held with partners outside Europe
  • Short courses (three hours) held on location at major conferences

Please check the Training page for the next events relevant to you.

If a higher level of design expertise is needed, professional design services may also be appropriate. Professional design support tailored to the JePPIX platform capability is offered by:

3. CAD software tools

A number of JePPIX partners develop computer aided design (CAD) software packages for PIC design which support the JePPIX PDKs. This means that the tools give improved levels of predictive quality. Vendors with JePPIX specific support include:

  • Filarete: ASPIC is a dedicated PIC simulator which is compliant with the PDAFlow standard.
  • PhoeniX Software: OptoDesigner 5 focuses on the physical layer of your design activities with powerful mode-solver and propagation capability
  • Photon Design: PicWave is a photonic circuit simulator capable of simulating both active and passive components in realistic detail which is coupled to JePPIX PDKs.

4. IP blocks

A number of basic building blocks and simple components are available in the software libraries. As in the electronic IC community, partners in the design community build upon this powerful platform to create advanced IP blocks - intellectual property. This can be an attractive way to accelerate designs with high performance and rugged components. The licensing terms for IP blocks will depend on usage. All building blocks and IP blocks are visible once the PDK is loaded into your design tool.

  • Bright Photonics has developed IP blocks in the BrightModules series.
  • VLC Photonics has developed over the years an extensive library of additional validated building blocks for all the JePPIX foundries

5. Layout tools for tape out

Layouts may initially be created schematically and these need to be converted to GDS-II format. Software vendors working with JePPIX align their tools with PDAflow to enable mask layer creation. Files are uploaded and checked for compliance.

  • Phoenix Software Mask Engineer enables JePPIX users to convert their circuit schematics to mask layout representation.
  • Nazca is an open-source Photonic IC design tool for professional GDS-II mask layout creation