Direct link to latest MPW schedules: Fraunhofer HHI, Smart Photonics, Lionix International


The JePPIX MPW Platforms

JePPIX offers platforms created from InP integrated photonics and the TriPleX platfrom, although not Silicon photonics. Each has there own distinctive advantage and a comparison table is offered below. Select the technology that suits your needs best. If you have an idea on what building blocks are required for your circuit, use the comparison table below to help you in your selection. JePPIX members receive independent advice to help in making the right selection. Contact the JePPIX MPW coordinator to discuss the possibilities and help you make your selection.

Technology Comparison Chart

TriPlex platform:

The TriPleX platform offers low-loss straight waveguides, bends, S-bends, offsets, splitters, spot size converters, lateral tapers and thermo-optic phase shifters. For example, combinations of these building blocks allow the creation of microwave photonics ASPICs by combining Mach-Zehnders and micro ring resonators. The current platform has guaranteed losses below 0.5 dB/cm. Further technical information on Triplex MPW's is posted on the new Lionix International website

InP platform

JePPIX offers a low cost brokering procedure for the production of InP based chips. InP offers amplification and laser sources which are monolithically integrated within the chip. No need for complex assembly steps. Additionally InP offers efficient modulators and detectors as well as a broad range of passive waveguide structures and devices. The latest capability overview is shown below. 

Component

Specification

HHI

Smart Photonics

Lasers and Amplifiers

 

 

 

SOA

Gain

92 cm-1@7000A/cm2

70 cm-1 @ 9000 A/cm2

 

Saturation Power

3dBm

t.b.d.

DBR grating

Tuning range

4 nm

*

DFB laser

Tuning range

4 nm

*

 

Output power

3 mW @ 150 mA

 

DBR laser

Tuning range

4 nm

*

 

Output power

3.5 mW @ 150 mA

 

Isolation section

 

yes

yes

 

 

 

 

Broad band reflectors

 

 

 

1x2 MMI reflector

Loss

*

2 dB

 

Reflectivity

 

40%

1x1 MMI reflector

Loss

*

2 dB

 

Reflectivity

 

70%

 

 

 

 

Polarization devices

 

 

 

Polarization splitter

Loss

<4 dB

*

 

Max polar ratio

25 dB

 

Polarization converter

Loss

<3 dB

*

 

Extinction

>10 dB

 

 

 

 

 

PIN photodiode

 

 

 

 

3 dB bandwidth

>35 GHz

10 GHz

 

Dark current

10 nA @ -2 dV

50 nA @ -2 V

 

sensitivity

0.8 A/W

0.8A/W

 

 

 

 

Modulators

 

 

 

Thermo-optic phase modulator

Loss

2 dB/cm

*

 

I(PI) x L

20 mA x mm

 

Current injection phase modulator

Loss

2dB for 100-200 um

<0.5dB for 2mm

 

I(PI) x L

20 mA x mm

t.b.d.

Electro-Optical phase modulator

Loss

*

<0.5dB for 2mm

 

Bandwidth

 

15 GHz

 

U(PI) x L

 

2-2.5 V x mm

 

 

 

 

Spot size converter

 

 

 

 

 

yes

lateral taper

Passive waveguides

 

 

 

Straight Waveguide

Loss

<2 dB/cm

3-4 dB/cm

Arc waveguide

Minimal radius

150 um;

100 um

Tapered waveguide

Loss

2dB/cm

?

 

 

 

 

Couplers:

 

 

 

1x2 MMI coupler

Loss

<1 dB

<1 dB

2x2 MMI coupler

Loss

<1 dB

<1 dB


Ordering your own chips

JePPIX offers one-stop technology access for InP and Triplex integrated photonics. Depending on your specific needs, the precise JePPIX partners involved will be different. 

The MPW Production Process

Speed up your MPW experience by downloading the easy manual of InP/SiNx MPW runs here

Compilation of forms you will need to fill for an MPW run:

 

Fraunhofer HHI 2017 MPW Schedule

 

Fraunhofer HHI InP Tx-Rx platform

Tx-Rx platform with passives, MMIs, AWGs, pin detectors, SOAs, DFB lasers, DBR gratings, polarization converters / splitters, spot size converters and thermo-optic phase shifters. As from October 2016, HHI has switched to MPW scheduled every three months as follows:

Run ID

Design Submission Deadline

Mask Tape-Out

Expected Delivery

Status

HHI05

15-Oct-2016

23-Oct-2016

Mid-June-2017

delivered

HHI06

15-Jan-2017

22-Jan-2017

Mid-August-2017

in fab

HHI07

16-Apr-2017

23-Apr-2017

end September 2017

in fab

HHI08

16-Jul-2017

23-Jul-2017

30-Oct-2017

CLOSED

HHI09

15-Oct-2017

22-Oct-2017

30-Jan-2018

open for registration

 

SMART Photonics 2017 MPW Schedule

RUNID

DESIGN SUBMISSION DEADLINE

MASK TAPE-OUT

PDK VERSION

EXPECTED DELIVERY

STATUS

BROKER

SMART18

15 August 2016

31 August 2016

SMART 5.x

2 January 2017

Delivered

JePPIX

SMART19

1 December 2016

15 December 2016

SMART 5.x

1 June 2017

Ready for shipment

JePPIX

SMART20

1 April 2017

15 April 2017

SMART 5.x

1 August 2017

In Fab

JePPIX

SMART21

1 June 2017

16 June 2017

SMART 5.x

1 October 2017

Open for registration

JePPIX

SMART22

1 September 2017

15 September 2017

To be determined

1 Jan 2018

Open for registration

JePPIX

SMART23

1 December 2017

15 December 2017

To be determined

1 April 2018

Open for registration

JePPIX

 
 

LioniX International 2017 MPW Schedule 

LionIX International

LioniX International is a leading global provider of customized microsystem solutions, in particular integrated photonics-based, in scalable production volumes. We provide customized solutions for OEM’s and system integrators from design to fully assembled modules. LioniX International B.V. is a private company, established in April 2016, following the acquisition of SATRAX B.V., XiO Photonics B.V. and LioniX B.V. 

For more detailed technical information, please click through to this MPW entry on the LioniX website.

This is the current MPW schedule for 2017.

11th run

12th run

13th run

Training

30 September 2016

28 February 2017

30 June 2017

Tape out

31 December 2016

31 May 2017

31 October 2017

Devices ready

30 April 2017

30 September 2017

28 February 2018

 

 

 

Design Flow

 

Process Design Kits

Process design kits (PDKs) are defined for each foundry. These are connected to commercial software packages to enable designers to create sophisticated photonic integrated circuits in a coherent design flow. The design kit includes

  • Design rules and mask layer information
  • Library of validated and parameterized components (for circuit design) 
  • Simulation models and measurements data (passive and active building blocks BBs) 
  • Die and package templates

1. Circuit function and platform selection

Designers start from a functional requirement, and then identify the Building Blocks which are needed to enable and evaluate this function in one chip. The most appropriate platform can usually be identified by inspecting the building block performance published here. Further information may also be available from the JePPIX coordinator.

 

2. Circuit design

Designers can develop their own understanding of the design possibilities and create their own chip layouts. JePPIX partners provide regular training sessions for MPW customers, both for specific CAD tools, and also as coherent JePPIX training events. Training events are organized throughout the year in three formats

  • JePPIX flagship two-week PIC designer training event in Eindhoven, NL each fall
  • One week PIC designer training events held with partners outside Europe
  • Short courses (three hours) held on location at major conferences

Please check the Training page for the next events relevant to you.

If a higher level of design expertise is needed, professional design services may also be appropriate. Professional design support tailored to the JePPIX platform capability is offered by:

3. CAD software tools

A number of JePPIX partners develop computer aided design (CAD) software packages for PIC design which support the JePPIX PDKs. This means that the tools give improved levels of predictive quality. Vendors with JePPIX specific support include:

  • Filarete: ASPIC is a dedicated PIC simulator which is compliant with the PDAFlow standard.
  • PhoeniX Software: OptoDesigner 5 focuses on the physical layer of your design activities with powerful mode-solver and propagation capability
  • Photon Design: PicWave is a photonic circuit simulator capable of simulating both active and passive components in realistic detail which is coupled to JePPIX PDKs.

4. IP blocks

A number of basic building blocks and simple components are available in the software libraries. As in the electronic IC community, partners in the design community build upon this powerful platform to create advanced IP blocks - intellectual property. This can be an attractive way to accelerate designs with high performance and rugged components. The licensing terms for IP blocks will depend on usage. All building blocks and IP blocks are visible once the PDK is loaded into your design tool.

5. Layout tools for tape out

Layouts may initially be created schematically and these need to be converted to GDS-II format. Software vendors working with JePPIX align their tools with PDAflow to enable mask layer creation. Files are uploaded and checked for compliance.

  • PhoeniX Softwares Mask Engineer enables JePPIX users to convert their circuit schematics to mask layout representation.